We are hiring for one of our reputed clients for the following position. If you're interested and your experience matches the requirement, we'd love to hear from you.
Position:RTL Design Engineer 2
Experience: 3-6 Years
Location: HYDERABAD
Contract 12 Months
Role & responsibilities
- Develop synthesizable Verilog/SystemVerilog RTL for digital IPs and subsystems.
- Perform IP and subsystem integration in ASIC/SoC environments.
- Work on AMBA protocols AXI, AXI4-Lite, AHB, and APB.
- Drive RTL quality checks including Lint, CDC, RDC, X-propagation, structural checks, and synthesis.
- Analyze and close CDC/RDC violations and ensure proper clock/reset domain handling.
- Perform RTL reviews and resolve functional, structural, and methodology issues.
- Ensure RTL handoff readiness, including clean Lint/CDC/RDC and synthesis-ready RTL.
- Validate register specifications, clock/reset architecture, and protocol compliance.
- Develop TCL/Python or scripting automation for quality checks, reports, and regression analysis.
- Collaborate with Architecture, DV, and Physical Design teams to resolve design issues and ensure quality signoff