- Perform full chip / block-level Physical Design (PNR) activities
- Work on floorplanning, placement, CTS (Clock Tree Synthesis), routing, and optimization
- Handle timing closure and congestion analysis
- Perform physical verification checks (DRC, LVS, IR drop, EM analysis)
- Collaborate with RTL, STA, and DFT teams for design convergence
- Work on low power techniques and multi-voltage designs
- Ensure design meets performance, power, and area (PPA) targets
Required Skills:
- Solid experience in Place & Route (PNR) flow
- Hands-on with tools like Cadence Innovus / Synopsys ICC2
- Good knowledge of STA concepts
- Experience in advanced nodes (7nm / 5nm / 3nm is a plus)
- Understanding of physical verification (DRC/LVS)
- Scripting knowledge (TCL / Python) is an added advantage
📌 PNR (India)
🏢 Neurealm
📍 India
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