Lead Physical Design Engineer

Location: Bengaluru

Experience: 6–10 Years

Role Overview

We are looking for a robust Lead Physical Design Engineer with hands-on expertise in full-chip physical implementation and Cadence Innovus. The role involves driving physical design from netlist to signoff for complex SoC designs.

Key Responsibilities
Own full-chip physical design from floorplanning through placement, CTS, routing, optimization, and physical signoff.
Drive timing, congestion, power, area, and QoR closure across PVT/MMMC scenarios.
Hands-on expertise in Cadence Innovus for implementation and optimization.
Perform STA correlation, timing closure, ECO implementation, and design convergence.
Work on clock tree synthesis, CTS optimization, routing, signal integrity, IR/EM, and physical verification.
Debug complex design issues and collaborate with RTL, STA, DFT, PD,



and signoff teams.
Develop automation using Tcl/Python/Perl to improve PD flows and productivity.

Required Skills
6–10 years of hands-on Physical Design experience.
Strong full-chip SoC implementation experience.
Excellent hands-on expertise in Cadence Innovus.
Solid understanding of floorplanning, placement, CTS, routing, timing and congestion closure.
Positive knowledge of MMMC, STA, ECO, physical verification, IR/EM and signoff flows.
Strong ownership, debugging and cross-functional collaboration skills.

Preferred
Experience with advanced-node SoCs and high-performance designs.
Exposure to Tempus, Voltus, Calibre and signoff methodologies.

📌 Lead Physical Design Engineer Bengaluru (India)
🏢 leadsoc technologies
📍 India