Senior Design Verification Engineer

Location: Bengaluru

Experience: 6–10 Years

Role Overview

We are looking for a Senior Design Verification Engineer with strong expertise in UCIe, Chiplet architectures, PCIe/CXL protocols, and end-to-end SoC/IP verification.

Key Responsibilities
Own verification of UCIe-based chiplet designs, covering FDI/RDI interfaces and protocol/data-path behavior.
Develop scalable SystemVerilog/UVM testbenches, test plans, checkers, scoreboards, assertions, and functional coverage.
Verify PCIe/CXL over UCIe, including protocol transactions, error handling, link behavior, and interoperability scenarios.
Drive constrained-random, directed, assertion-based, and coverage-driven verification.
Debug complex RTL/protocol issues across simulation, regressions, and waveform analysis.
Collaborate closely with RTL, architecture, firmware,



and post-silicon teams to close verification gaps.

Required Skills
6–10 years of hands-on Design Verification experience.
Robust SystemVerilog, UVM, SVA, and verification methodology expertise.
Deep understanding of UCIe – FDI/RDI, chiplet architectures, and die-to-die communication.
Hands-on experience with PCIe and/or CXL, preferably deployed over UCIe.
Solid protocol-level debugging and coverage closure skills.
Experience with industry-standard simulation and debug tools.

Good to Have
UCIe compliance/interoperability or multi-die SoC verification experience.
Experience with PCIe/CXL protocol checkers, VIPs, and formal verification.
Robust Python/Perl/Tcl scripting for verification automation.

📌 Senior Design Verification Engineer Bengaluru (India)
🏢 leadsoc technologies
📍 India