Hi,Good Day to you!JOB DESCRIPTION::ASIC/SoC Design position is your prospect to join one of the industry’s leading companies in Smart Edge SoCs for network/systems control, management security systems, and IIoT. You should have prior knowledge of logic design and computer architecture.Skills:Microarchitecture, PCIe, USB, Ethernet, DDR3/4, LPDDR, AXI, I2C/I3C, SPI, SD/SDIO/eMMC, UART, PTPX, Optimisation, 2/3/4/5/6nm nodes.We are looking for candidates with 7–20 years of experience who can join with us and part of ODC long term project.Roles & Responsible::Write design specifications for different functional blocks on a chip, create micro-architecture diagrams of functional blocks, design functional blocks using System Verilog RTL code, and conduct synthesis and route to meet timing / area goalsSynthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting,



Static Timing Analysis (STA)Contribute to Design Verification, Synthesis, Power Reduction, Timing Convergence & Floorplan effortsResponsible for logic implementation of complex design block(s) using RTL coding techniques (Verilog)Code Verilog RTL for high performance designs with supervision from manager and input from peers and architects in the engineering teamYou handle Verilog RTL logic design and debugDevelop RTL for logic blocks and participate in Front End activities like Synthesis, Timing Closure & FPGA implementationContribute as a design engineer developing the next-generation of multi-core processorsSpecify, design, and synthesize RTL blocks, optimize and floorplan themWork with verification engineers to ensure accuracy.Thanks,P Mohankrishna,[email protected]

📌 Senior Design Engineer (Bengaluru)
🏢 Eximietas Design
📍 Bengaluru