Lead Design EngineerAs an

RTL Design Lead , you will play a critical role in leading the RTL design and verification process for complex

digital designs . You will manage a team of

RTL engineers , collaborate with cross-functional teams, and ensure the successful implementation of high-performance, low-power designs. The ideal candidate should have a strong technical background in

RTL design , experience in

digital design flow , and the ability to lead a team towards the successful execution of complex projects.

Key Responsibilities:RTL Architecture and Design:

Lead the RTL design of complex digital systems, including

microprocessors ,

ASICs ,

FPGA designs , and

system-on-chip (SoC)

components.Team Leadership:

Manage and mentor a team of

RTL design engineers , providing technical guidance, training, and fostering a cooperative team environment.Design Specifications:

Work closely with

system architects

and

hardware engineers

to define design specifications, ensuring the implementation meets performance, area, and power requirements.RTL Coding:

Write and review

high-quality RTL code

in

Verilog ,

SystemVerilog , or

VHDL , focusing on scalability, reusability, and modularity.Design Validation:

Lead the development of testbenches and collaborate with verification teams to ensure the design is thoroughly verified using

simulation ,

formal verification , and

coverage analysis .Timing and Performance Optimization:

Drive performance and timing closure by working with design and implementation teams to address critical paths and optimize the design for

low power ,

high speed , and

minimal area .Integration:

Lead the integration of RTL design blocks into larger systems, ensuring smooth handoffs between various teams, including

digital, analog , and

software

teams.Mentorship and Collaboration:





Provide mentorship to junior engineers and collaborate with cross-functional teams, including

verification ,

software , and

physical design

teams to ensure the design meets all system requirements.Documentation and Reporting:

Ensure the proper documentation of design flows, methodology, and processes, including regular design reviews and progress reports to management.Continuous Improvement:

Drive continuous improvement in RTL design methodologies, best practices, and tools. Stay up to date with the latest trends and technologies in

RTL design

and

digital systems .

Required Qualifications:Bachelor’s or Master’s degree

in

Electrical Engineering ,

Computer Engineering , or a related field.7+ years of experience

in

RTL design

for complex

digital systems , with at least

3+ years of leadership experience

in managing teams and projects.Expertise in

Verilog ,

SystemVerilog , or

VHDL

for RTL coding, with a strong understanding of

digital design principles .Proven experience in designing and verifying large-scale

SoC ,

ASIC , or

FPGA designs .Strong understanding of

digital design flow , including

synthesis ,

place-and-route ,

timing analysis , and

power optimization .Experience with

simulation and verification methodologies , including

UVM ,

SV-based testbenches , and

coverage-driven verification .Proficient in using

EDA tools

such as

Cadence ,

Synopsys ,

Mentor Graphics , or other RTL design and verification tools.Strong knowledge of

timing analysis ,

static timing analysis (STA) , and

power optimization techniques .Excellent problem-solving and debugging skills, with experience in addressing complex design issues.Strong

communication skills

with the ability to articulate technical ideas clearly and effectively to both technical and non-technical stakeholders.

Experience: 7 to 12 YearsLocation: Bangalore

📌 Lead Design Engineer (Mumbai)
🏢 ACL Digital
📍 Mumbai