Key Responsibilities Circuit Design Architecture Develop transistorlevel circuit designs for analog mixedsignal macros across advanced CMOS process nodes 28nm 16nm FinFET 7nm and below Architect and implement LDO regulators bandgap references and POR circuits with precision bias networks meeting tight temperature supply and process variation targets Design highspeed receiver RX frontends clockdata recovery CDR loops DLL and PLL circuits targeting multiGbps serial interface standards Implement transmitter TX drivers with programmable swing preemphasis and equalization for PCIe USB MIPI DDR and custom SerDes links Design DCDC switching converters charge pumps and analog switch circuits optimized for efficiency area and EMI compliance Develop oscillator circuits ring relaxation LC and clocking distribution networks meeting phase noise jitter and dutycycle specifications Design undervoltage and overvoltage protection circuits including supervisory functions brownout detection and softstart control Create bias generator networks current references and commonmode feedback circuits supporting systemlevel analog infrastructure Simulation Verification Perform comprehensive SPICElevel simulations DC AC transient noise Monte Carlo and corner analysis using Cadence Spectre HSPICE or equivalent Conduct behavioral modeling in VerilogA VerilogAMS to enable systemlevel mixedsignal cosimulation Execute process voltage and temperature PVT corner verification to guarantee robust firsttime silicon success Perform postlayout simulation with extracted parasitics RC RLC and validate performance degradation vs schematic targets Collaborate with physical design layout engineers to review parasitic impact and guide layout techniques shielding symmetry matching Generate and maintain comprehensive simulation decks and regression test benches for IP reuse and future node porting Specification Documentation Review Author detailed circuit design specifications schematic documentation and simulation result reports Participate in and lead design reviews peer reviews and architectural tradeoff analyses Interface with system architects and SoC integration teams to define blocklevel requirements and pin specifications Support IP characterization datasheet generation and application note creation Silicon Validation BringUp Develop bench test plans and support silicon bringup and characterization of firstpass prototypes Analyze measured silicon data vs simulation predictions identify failure modes and drive rootcause analysis Propose and implement design fixes and revision updates based on silicon findings Work with test engineering teams to develop automated production test solutions ATE for manufactured silicon Collaboration Mentorship Work in close partnership with layout engineers DFT engineers and SoC integration teams throughout the full design cycle Mentor junior circuit designers and contribute to engineering capability building within the team Participate in foundry interactions PDK evaluations and device model reviews Required Qualifications Bachelor of Science in Electrical Engineering BSEE Mandatory Minimum 3 years of qualified experience in analog mixedsignal IC circuit design Proficiency with Cadence Virtuoso Schematic Editor and Analog Design Environment ADEL XL GXL Handson SPICE simulation experience using Spectre HSPICE or Eldo including Monte Carlo and PVT corner analysis Demonstrated design experience with at least 3 of the macro categories listed in the Circuit Design Scope section Solid understanding of MOSFET device physics noise analysis stability phase margin and mismatch variation effects Familiarity with FinFET or advanced CMOS process node design constraints and device models Knowledge of analog design fundamentals opamp topologies feedback theory frequency compensation and bandgap references Preferred Qualifications Experience with highspeed serial interface standards PCIe Gen 4 5 USB 3 x 4 DDR5 MIPI or custom SerDes at 10112 Gbps Proficiency in VerilogA VerilogAMS behavioral modeling for systemlevel mixedsignal simulation Prior collaboration with foundries such as TSMC Samsung GlobalFoundries or Intel Foundry