TITLE: RTL DESIGN ENGINEER(SMTS)

nLOCATION: GREATER BENGALURU AREA

nCompany Description

nAt Tsavorite Scalable Intelligence, we are pioneering the semiconductor industry's first Omni Processing Unit (OPU)—a breakthrough composable architecture designed to power the next generation of real-time, multi-modal Agentic AI.

nFounded in 2023 by a veteran team from Intel, Nvidia, Qualcomm, and Apple, we are on a mission to eliminate the cost, power, and complexity bottlenecks of legacy GPU systems. Our technology delivers a 10x performance gain at 10% of energy consumption, scaling seamlessly from edge devices to exascale data centers.

nWhy Engineers Join Us:

n

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- Architectural Innovation: Work on the MultiPlexusTM fabric, a revolutionary interconnect offering petabyte-scale bandwidth and ultra-low latency.
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- Full-Stack Impact: We are building everything from modular chiplets on Samsung's SF4X platform to our Tsavorite AI Orchestration Stack (TAOS), which provides zero-switching-cost compatibility for CUDA-optimized workflows.
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- Market Momentum: We emerged from stealth with over $100 million in pre-orders from Global 500 companies and sovereign cloud providers.
n

nKey Links to Include

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- Official Website: tsavoritesi.com
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- LinkedIn Page: Tsavorite Scalable Intelligence | LinkedIn
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- Recent News: Tsavorite Emerges with $100M in Orders & 10x Performance (Forbes)
n

nJOB DESCRIPTION:

nJob Title: Design Engineer (Front-End/RTL)

nRole Overview

nAs a Design Engineer, you will be the bridge between high-level architecture and physical

nimplementation. You will own the development of critical SoC subsystems/IPs, translating

ncomplex architectural requirements into productive, high-performance RTL. This role requires

nsomeone who thrives on solving complex design challenges and can maintain design integrity





nthrough the rigors of synthesis, timing, and verification.

nKey Responsibilities

n- Micro-architectural Definition: Translate high-level architectural requirements into

nrobust, detailed micro-architectural specifications.

n- Design & Implementation: Develop high-quality, synthesizable RTL using Verilog and

nSystemVerilog, ensuring designs meet performance, power, and area (PPA) targets.

n- Strategic Analysis: Conduct deep-dive analyses of implementation options, weighing

ntrade-offs between latency, throughput, and silicon real estate.

n- Full Front-End Flow: Drive the design through the ASIC front-end suite, including

nSynthesis, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC).

n- Timing Ownership: Take responsibility for timing closure to ensure the design meets

nfrequency targets across all corners.

n- Cross-Functional Collaboration: Manage design iterations by working closely with the

nVerification team and the Physical Design team

n- Debugging: Root-cause complex issues across simulation, linting, CDC, and synthesis

nenvironments.

nRequired Qualifications

nEducation & Expertise

n- Degree: Bachelor's or Master's degree in EC/EE/CS or a related field.

n- Experience: 8-14+ years of proven experience in SoC or Subsystem-level design.

n- Good understanding of the AMBA protocols, specifically CHI, AXI, AHB, and APB.

n- Expert-level proficiency in Verilog/SystemVerilog and micro-architecture development.

n- Hands-on experience with CDC/RDC tools, Linting, and Logic Synthesis (e.g., Design compiler, Genus).

n- Strong proficiency in Static Timing Analysis (STA) and timing constraints

n- Good understanding of ARM architecture is desirable.

n- Strong communication skills to articulate complex technical trade-offs to stakeholders

nUday

[email protected]

nwww.mulyatech.com

n"Mining the Knowledge Community"

📌 RTL Design Engineer-SMTS (Bengaluru)
🏢 Tsavorite Scalable Intelligence
📍 Bengaluru