RTL Design Engineer | 5-10 Years Experience /n Job Summary /n We are looking for a skilled RTL Design Engineer with 5-10 years of experience in ASIC/SoC development. The ideal candidate will be responsible for designing, coding, and validating complex digital designs, working closely with cross-functional teams to deliver high-quality silicon solutions. /n Key Responsibilities /n /n
- Develop and maintain RTL designs using Verilog/SystemVerilog or VHDL.
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- Perform functional verification and debugging of digital designs through simulation and formal verification techniques.
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- Participate in design reviews and ensure compliance with RTL coding standards and best practices.
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- Support timing analysis, timing closure, and constraint development using SDC.
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- Collaborate with Verification, Synthesis, Physical Design, and Architecture teams throughout the design lifecycle.
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- Analyze and resolve design, functionality, and timing-related issues.
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- Contribute to successful SoC/ASIC integration and tape-out activities.
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- Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
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- 5-10 years of hands-on RTL design experience in ASIC/SoC development.
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- Strong proficiency in Verilog/SystemVerilog or VHDL.
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- Solid understanding of digital design fundamentals, including:
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- Combinational and Sequential Logic
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- Finite State Machines (FSMs)
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- Timing Analysis and Clocking Concepts
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- Experience with RTL verification and debugging.
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- Knowledge of SDC constraints and timing closure methodologies.
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- Strong analytical, problem-solving, and debugging skills.
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- Excellent communication and teamwork abilities.
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- Exposure to UVM-based verification environments.
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- Experience with synthesis, STA, and ASIC design flows.
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- Scripting knowledge in Python, Perl, or Shell.
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- Experience with industry-standard EDA tools.
/n /n Why Join Us? /n /n
- Opportunity to work on advanced ASIC/SoC technologies.
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- Collaborative and innovation-driven engineering environment.