KEY RESPONSIBILITIES :

- Responsible for Multi Voltage domain STA workplace setup, execution and timing closure.
- Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks.
- Ensuring timing correlation between PnR STA and timely feedbacks to PD team.
- Generating block level HS session and using Top context from SoC for Block-SoC Interface timing closure.
- Generating timing ECO using Tweaker/PrimeClosure.

Requirement :

- 5 years of experience in timing closure of high frequency blocks (> GHz range).
- Analyzing the timing reports and identifying both design and constraints related issues.
- Worked on blocks with multiple power and voltage domains.
- Preferred EDA tool experience : Primetime, Tweaker/PrimeClosure, Innovus.
- Strong Understanding of DFT modes requirements for timing signoff.
- Good understanding of physical design flow and ECO implementation.
- Strong understanding of SDC constraints, OCV, AOCV, POCV analysis.
- Strong TCL/scripting knowledge is mandatory.

📌 Leadsoc Technologies - Lead STA Engineer (India)
🏢 LeadSoc Technologies India
📍 India