Build the silicon. Own the problem. Grow with AionSi.

We are building experienced engineering teams for technically demanding semiconductor programs. Bring depth in your discipline and take ownership from engineering execution through closure.

Experienced engineers can own defined workstreams, technical decisions and delivery outcomes across the semiconductor lifecycle.

Current engineering opportunities

These roles reflect the current approved hiring requirements. AionSi may update openings as the engineering roadmap evolves.

SoC DV Manager

Hyderabad Lead SoC design verification programs with solid team leadership, verification strategy and delivery ownership.

CORE Responsibilities

- Lead SoC design verification strategy, execution and closure.
- Own verification planning, technical reviews, debug and delivery milestones.
- Build and mentor a strong design verification engineering team.

Required / Preferred

- SoC Design Verification
- SystemVerilog / UVM
- Technical Leadership
- Verification Closure

Experience: 3+ years

Emulation Engineer

Join the emulation team to develop, debug and execute complex SoC emulation flows.

CORE Responsibilities

- Work on SoC emulation environments and execution flows.
- Debug emulation failures and collaborate with design and verification teams.
- Contribute to reliable emulation bring-up and execution methodology.

Required / Preferred

- Emulation
- SoC Verification
- Debug
- Semiconductor Design Flows

Experience: 2-5 years

Digital Marketing Executive

Bengaluru Build digital visibility and demand-generation programs for AionSi in the semiconductor technology market.

CORE Responsibilities

- Execute digital marketing programs across relevant channels.
- Create and coordinate semiconductor-focused content and campaigns.
- Support lead generation, analytics and campaign performance tracking.

Required / Preferred

- Digital Marketing
- B2B Technology Marketing
- Content Campaigns




- Semiconductor / Technology

Experience: 5-8 years

Physical Verification Engineer

Bengaluru and Hyderabad Own sign-off physical verification for advanced-node designs and ensure tape-out-ready quality.

CORE Responsibilities

- Perform DRC, LVS and ERC verification for advanced technology nodes.
- Drive physical sign-off checks and closure toward tape-out.
- Work closely with design, layout and foundry teams to resolve verification issues.

Required / Preferred

- DRC
- LVS
- ERC
- Physical Sign-off
- Advanced Technology Nodes

Experience: 5+ years

DV Engineer

Develop and debug UVM-based verification environments and drive regression and coverage closure.

CORE Responsibilities

- Develop and maintain UVM testbenches.
- Debug regressions and verification failures.
- Drive functional coverage closure and verification deliverables.

Required / Preferred

- SystemVerilog
- UVM
- AMBA Protocols
- Regression Debug
- Coverage Closure

Physical Design III

Own physical-design execution from planning through tape-out, including implementation, verification, reviews and technical leadership.

CORE Responsibilities

- Deliver fully verified physical designs at IP and top-level.
- Manage the physical-design phase from planning and requirements through tape-out.
- Own documentation, reviews, quality, progress and technical coordination.
- Lead physical designers and participate in improvement and knowledge-driven meetings.

Required / Preferred

- Cadence
- Virtuoso
- Physical Design
- High Frequency / mmWave

Experience: 4+ years

DFT Engineer

DFT Engineer Execute DFT insertion, MBIST, JTAG, ATPG and manufacturing-test verification flows.

CORE Responsibilities

- Hands-on MBIST and JTAG insertion.

Disclaimer: This has been sourced from a public domain and may have been modified by Naukri.com to improve clarity for our users. We encourage job seekers to verify all details directly with the employer via their official channels before applying.

📌 Experienced Engineers (Bengaluru)
🏢 AIonSi
📍 Bengaluru