Principal Accountabilities

1. Analog designer with experience of 5 to 10 Years of experience in below,

2. CT sigma delta ADC, RFIC design: LNA and mixer, PLLs

3. Circuit Architecture & Design:

Architect and design high-performance analog/mixed-signal building blocks (e.g., PLLs, ADCs/DACs, RFIC).

4. EDA exposure:
Custom Design/Schematic: Cadence Virtuoso (ADE/Maestro).

Simulation: Spectre, HSPICE, or CustomSim.

Physical Verification: Mentor Calibre (DRC/LVS/PEX) or Synopsys IC Validator. Reliability/Sign-off: Experience with Voltus, RedHawk, or similar power/IR integrity tools

5. Multi-Node Design:

Translate and optimize designs across different process geometries, including transition strategies from

Planar (e.g., 28nm)

to

FinFET (e.g., 16nm, 7nm…)

nodes.

6. Simulation & Verification:

Perform comprehensive pre-layout and post-layout simulations, including Monte Carlo, corner analysis, noise analysis, and reliability modeling (EM/IR/Aging/BTI/HCI).

7. Methodology:
Drive best practices in analog design methodology, including the adoption of automated design tools and script-based verification (Python/SKILL/Tcl).

📌 Analog Design Engineer (Bengaluru)
🏢 eInfochips (An Arrow
📍 Bengaluru