We are seeking a highly skilled Physical Design Engineer to own the RTL to GDS physical implementation flows for high-performance and low-power designs. You will be responsible for synthesis, floor-planning, place and route, clock tree synthesis, timing and power closure, EM/IR, PDV, and final PD sign-off. This role requires deep collaboration with micro-architects, expertise in physical design tools, and a strong understanding of modern sub-micron technology nodes.

Roles and Responsibility:

- Own RTL to GDS physical implementation flows for synthesis, floor-planning, place and route, clock tree synthesis, timing & power closure, EM/IR, PDV, and final PD sign off.
- Own physical design & implementation of high-performance designs from block level to system level components.
- Deep collaboration with Micro-architects to explore performance, power and area (PPA) trade-offs for high performance and low power designs.
- Conduct physical implementation feasibility studies and provide design recommendations for best PPA.
- Develop methodologies and recipes for various stages of physical implementation.
- Perform various physical design validation (PDV) flows for Timing, Power, EM/IR, etc., to ensure physical design quality.
- Perform design rule checking (DRC),



LVS (Layout Versus Schematic) checks, and other physical verification tasks.

Qualifications and Preferred Skills:

- Experience in all aspects of physical design including synthesis, floor planning, place & route, timing & power closure, EM/IR, physical design validation, etc.
- Experience with synthesis, place & route, static timing analysis and PDV tools.
- Experience in implementing clock trees and power grids.
- Experience with scripting for physical design flow automation.
- Experience with Synopsys tools such as Design Compiler, Prime Time, ICC, Fusion Compiler, etc.
- Positive knowledge of high-performance and low-power microarchitecture and logic design principles.
- Understanding of modern (sub 7nm) sub-micron technology nodes and device physics.
- Basic knowledge of System/SoC Architecture and System Verilog RTL coding.
- Strong communication and collaboration skills.

QUALIFICATION:

- BS, MS in Electrical Engineering or Computer Engineering or related degree.

Skills: synopsys tools , Scripting, Soc Architecture, Design Principles, Physical Design, Microarchitecture

Experience: 2.00-4.00 Years

📌 Physical Design Engineer (Bengaluru)
🏢 Aritha
📍 Bengaluru