Required Skills -
Robust understanding of advanced STA concepts and challenges in advanced technology nodes such as 5nm, 3nm and 2nm. Thorough knowledge of the ASIC design cycle and timing closure flow and methodology. Proficiency in timing constraints and timing closure. Expertise in STA tools (any of Primetime, Tempus, Tweaker) and flow. Proficiency scripting languages (TCL, Perl, Python). Solid background in Implementation and Extraction domain.