Architect and implement DFT strategies for advanced Custom SoC designs. Collaborate with Design, Verification and Implementation teams to ensure DFT requirements are met. Perform scan insertion, ATPG pattern generation, and BIST (Memory and Logic) implementation. Perform DFT simulations and analyze results to ensure test coverage and quality. Debug and resolve DFT-related issues throughout the design process. Mentor junior engineers and provide technical guidance as needed.
Identify
Test time optimization opportunities.
Must-Have
Well versed in Verilog/VHDL RTL coding, experienced in using Mentor DFT, Cadence and Synopsys EDA tools. Hands-on experience in scan insertion, JTAG, LBIST, ATPG DRC and coverage analysis,
Simulation debug with timing/SDF. Must have worked on few SoC DFT effort at least, from start to end. Must be proactive, team-oriented and detail-oriented capable of exercising independent judgment. Strong expertise in Post Silicon Readiness (Pattern Generation) and Silicon Debug.
Positive to Have
Excellent understanding of logic design fundamentals and gate/transistor level implementation. Prior experience working on high performance technology nodes and understanding of deep sub-micron design problems/solutions. Robust problem solving and debug skills across various levels of design hierarchies.