Our vision is to transform how the world uses information to enrich life forall .

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
To be part of a highly skilled and challenging high speed DDR & ONFI PHY design team working on the newest technology nodes
UVM-AMS Integration: Design scalable, reusable metric-driven verification environments using SystemVerilog/UVM combined with mixed-signal simulators.Real Number Modeling (RNM): Author precise and rapid behavioral models using SystemVerilog (EEnet/wreal) or Verilog-AMS to replace heavy SPICE sub-circuits, drastically accelerating chip-level verification.Full-Chip Co-Simulation: Bring up and support top-level gate-level simulations (GLS), power-aware verification (UPF/CPF), and mixed-signal co-simulations to catch interface bugs.
Responsible for overall IP and sub-system verification from test plan creation, UVM development to signoff.
Leading,



mentoring and coaching junior team members
Work closely with Digital and Analog designers

Skills Required:
Valuable experience of logic simulation, UVM workplace and testbench creation
Experience in AMS simulations
Understanding of Analog blocks like SDLL DCC Band gap
Experience with RTL debugging, score boarding and code coverage analysis
Understanding of DDR/LPDDR JEDEC or NAND ONFI and DFI protocols
Sound knowledge of Verilog and System Verilog languages
Exposure to modelling and validating complex analog circuits in Verilog and Verilog-A
M.S./M.Tech, BS/BE (Electronics)

Experience Required: 5+ Years

About Micron Technology, Inc.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

Micron Prohibits the use of child labor and complies w

📌 Staff Engineer Hyderabad
🏢 Micron
📍 Hyderabad