Job Description
RTL Design Engineer | 5-10 Years Experience

n Job Summary
nWe are looking for a skilled RTL Design Engineer with 5-10 years of experience in ASIC/SoC development. The ideal candidate will be responsible for designing, coding, and validating complex digital designs, working closely with cross-functional teams to deliver high-quality silicon solutions.
n Key Responsibilities
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- Develop and maintain RTL designs using Verilog/SystemVerilog or VHDL .n
- Perform functional verification and debugging of digital designs through simulation and formal verification techniques.n
- Participate in design reviews and ensure compliance with RTL coding standards and best practices.n
- Support timing analysis, timing closure, and constraint development using SDC .n
- Collaborate with Verification, Synthesis, Physical Design, and Architecture teams throughout the design lifecycle.n
- Analyze and resolve design, functionality, and timing-related issues.n
- Contribute to successful SoC/ASIC integration and tape-out activities.n

nRequired Qualifications
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- Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.n
- 5-10 years of hands-on RTL design experience in ASIC/SoC development.n
- Solid proficiency in Verilog/SystemVerilog or VHDL .n
- Solid understanding of digital design fundamentals, including:n
- Combinational and Sequential Logicn
- Finite State Machines (FSMs)n
- Timing Analysis and Clocking Conceptsn
- Experience with RTL verification and debugging.n
- Knowledge of SDC constraints and timing closure methodologies.n
- Strong analytical, problem-solving, and debugging skills.n
- Excellent communication and teamwork abilities.n

nPreferred Skills
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- Exposure to UVM-based verification environments .n
- Experience with synthesis, STA, and ASIC design flows.n
- Scripting knowledge in Python, Perl, or Shell .n
- Experience with industry-standard EDA tools.n

nW

📌 RTL Design Engineer (Noida)
🏢 HCLTech
📍 Noida