Job DescriptionExperience: 4-10 years
NLocation - Bangalore/Pune
NResponsibilities:
N· Complete DFT ownership of projects including:
N
- n
- Test architecturedefinition. N
- Identifying and implementing RTL changes for DFT. N
- Performing scan insertion, LEC checks, low power CLP checks. N
- Developing timing constraints for test mode timing closure. N
- Scan and ATPG for different fault models. N
- Boundary scan, ACJTAG, IEEE 1500 implementation and verification. N
- IEEE1687 (iJTAG) compliant ICL/PDL for functional manufacturing tests. N
- Running zero delay and timing simulations and debugging on all the above aspects. N
- Supporting post siliconbring up. N
- Interacting with customers on DFT aspects and support Marketing & Pre-Sales team. N
- Experience working on very high speed and low power designs N
📌 Lead Dft Design Engineer (Karnataka)
🏢 Cadence System Design and Analysis
📍 Karnataka
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