ASIC/SoC Design position is your chance to join one of the industry’s leading companies in Smart Edge SoCs for network/systems control, management security systems, and IIoT. You should have prior knowledge of logic design and computer architecture.

We are looking for candidates with 7–20 years of experience who can join with us and part of ODC long term project.

Write design specifications for different functional blocks on a chip, create micro-architecture diagrams of functional blocks, design functional blocks using System Verilog RTL code, and conduct synthesis and route to meet timing / area goals

Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Static Timing Analysis (STA)

Contribute to Design Verification, Synthesis, Power Reduction,



Timing Convergence & Floorplan efforts

Responsible for logic implementation of complex design block(s) using RTL coding techniques (Verilog)

Code Verilog RTL for high performance designs with supervision from manager and input from peers and architects in the engineering team

You handle Verilog RTL logic design and debug

Develop RTL for logic blocks and participate in Front End activities like Synthesis, Timing Closure & FPGA implementation

Contribute as a design engineer developing the next-generation of multi-core processors

Specify, design, and synthesize RTL blocks, optimize and floorplan them

design

📌 Design Engineer (Bengaluru)
🏢 Eximietas Design
📍 Bengaluru