Job Description (JD) : Design Verification Engineer (4+ Years Experience)
Position Overview: We are seeking a highly skilled and experienced Design Verification Engineer with over 4 years of experience, specifically in PCIe and/or CXL (Compute Xpress Link) IP and Subsystem verification, to join our innovative team. The ideal candidate will have a strong background in verification methodologies, System Verilog programming skills, excellent problem-solving skills, and the ability to work collaboratively in a quick-paced environment.
Key Responsibilities:
Develop and implement comprehensive verification plans for PCIe and/or CXL IP and Subsystem.
Create and maintain testbenches, test cases, and verification environments using System verilog and UVM methodology.
Perform functional verification of RTL designs, including simulation, debugging, and coverage analysis.
Collaborate with design engineers to understand design specifications and requirements for IP and subsystems.
Identify and resolve design and verification issues, ensuring high-quality and robust designs.
Generate and analyze verification metrics to track progress and ensure coverage goals are met.
Participate in design and verification reviews, providing technical expertise and insights.
Stay updated with the latest verification technologies and methodologies and apply them to improve verification efficiency and effectiveness.
Mentor junior verification engineers and provide technical guidance.
Qualifications:
Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related field.
4+ years of experience in design verification, with a focus on PCIe and/or CXL IP/Subsystem verification.
Knowledge of PCIe Gen5/Gen6 protocol is a plus.
Proficiency in verification languages and methodologies, such as System Verilog, UVM, and other industry-standard tools.
Strong understanding of digital design concepts, RTL coding, and simulation.
Experience with scripting languages (e.g., Pyt