Project Role : Design-For-Test (DFT) Engineer
Project Role Description : Enable effective post-manufacturing chip testing by integrating testability features during the design phase. Apply DFT methodologies such as scan chains, Built-In Self-Test (BIST), and boundary scan to detect defects and enhance test coverage. Ensure high-quality silicon by collaborating with design and verification teams to optimize for test efficiency and fault isolation.
Must have skills : Design for Testability (DFT)
Positive to have skills : NA
Minimum 3 year(s) of experience is required
Educational Qualification : 15 years full time education
Summary:
As a Design-For-Test Engineer, you will enable effective post-manufacturing chip testing by integrating testability features during the design phase. Your typical day will involve applying DFT methodologies such as scan chains, Built-In Self-Test, and boundary scan to detect defects and enhance test coverage. You will collaborate closely with design and verification teams to ensure high-quality silicon, optimizing for test efficiency and fault isolation,
while continuously seeking innovative solutions to improve testing processes and outcomes.
Roles & Responsibilities: -Tools proficiency – Tessent, VCS, Verdi, DC, PT
-Tessent tool for ATPG setup, DRC analysis, pattern generation for Stuck-at, TDF, PDF
-Scan compression and insertion techniques
-ATPG Timing and no-timing simulation
JTAG/IJTAG
-Pattern delivery and coverage sign-off
- Expected to perform independently and become an SME.
- Required active participation/contribution in team discussions.
- Contribute in providing solutions to work related problems.
- Engage in continuous learning to stay updated with the latest DFT methodologies and technologies.
- Assist in the development of test plans and strategies to ensure comprehensive test coverage.
Professional & Technical Skills: -Memory BIST and repair scheme implementation
-Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation