Design Verification Engineer (4-15 Years)
Mediatek is building Sub System DV teams in Bangalore to cater to the verification challenges in our next gen Smartphone, Compute and Automotive chips. We are seeking experienced Design Verification Engineers with 4-15 years of experience, specifically in subsystem verification or SoC verification, to join our highly talented verification team at Bangalore.
The candidate needs to have a strong background in Sub System verification methodology and flows. Should have exposure to different verification methodologies at Sub System or SoC Level. Experience in test planning & testbench design/improvements and coverage closure is needed. Low power verification exposure is a plus.
Must have strong System Verilog programming skills and experience with UVM methodology. Should possess excellent problem-solving skills and ability to work collaboratively in a fast-paced setting spanning across geographies.
Senior candidates with experience in leading teams will be considered for higher/lead roles.
Key Responsibilities:
Develop and implement comprehensive verification test plans for subsystems components and IP’s in those sub-system.
Build testbenches from scratch for new Sub systems, develop verification flows and test cases using System Verilog and UVM methodology.
Drive functional verification of RTL designs at Sub System level or SoC Level including simulation, debugging and coverage closure, ensuring high-quality and robust designs.
Collaborate with design engineers to understand detailed design specifications and target corner cases and various configurations of subsystem levels.
Generate and analyze verification metrics to regularly track progress and ensure timely coverage closure.
Participate in design and verification reviews, test plan reviews, methodology reviews, providing technical expertise and insights.
Incorporate newer verification techniques and methodologies to improve verification efficiency and effectiveness.
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