A Design for Testability (DFT) Engineer Core Responsibilities

- Scan Insertion: Add scan chains into the chip design to control and observe internal circuit nodes.

- ATPG Execution: Run Automatic Test Pattern Generation to create test vectors that check for stuck-at and transition faults.

- BIST Integration: Implement Memory Built-In Self-Test (MBIST) and Logic BIST blocks to test embedded memories and logic safely.

- Boundary Scan: Design JTAG and boundary scan architectures for board-level testing.

- Timing Closure: Work with static timing analysis (STA) to ensure DFT logic does not break normal chip performance.

- Gate-Level Simulation: Verify test patterns using industry simulators before sending the design to production. [1, 2, 3, 4, 5]

Key Technical Skills

- Methodologies: Scan, ATPG, MBIST, JTAG, and low-power DFT.

- EDA Tools: Proficiency in tools from major vendors like Synopsys, Cadence, or Mentor/Siemens (Tessent).

- Scripting Languages: Solid skills in Tcl, Perl, or Python for automation. [1, 2, 3]

Qualifications

- Education: Bachelor's or Master's degree in Electronics, Electrical Engineering, or VLSI design.

- Experience: Ranges from junior roles (3–5 years) to senior or lead positions requiring 7 to 15+ years of hands-on chip bring-up experience. [1, 2, 3, 4, 5]

If you'd like, let me know:

- Your years of experience

- Your primary EDA tools (Tessent, Synopsys, etc.)

A standardVLSI Physical Design (PD) Engineer (JD) Key Responsibilities

- Flow Execution: Perform full-chip or block-level Place and Route (PnR)



from RTL/synthesis handoff to final GDSII generation. [1]

- Floorplanning & Placement: Execute floorplanning, power grid planning, macro placement, and standard cell placement while managing core utilization and congestion. [1, 2]

- Clock Tree Synthesis (CTS): Build and balance clock distribution networks to minimize clock skew and latency. [1]

- Routing & Optimization: Run global and detailed routing, followed by physical and electrical optimization. [1, 2]

- Timing Closure: Analyze and fix setup and hold time violations using Static Timing Analysis (STA). [1]

- Sign-off Verification: Perform Design Rule Checking (DRC), Layout Versus Schematic (LVS), IR drop, electromigration, and antenna checks. [1]

Required Skills & Qualifications

- Education: B.Tech/M.Tech or equivalent in Electronics, Electrical Engineering, or Computer Science.

- Technical Knowledge: Strong foundation in digital VLSI design, semiconductor physics, and CMOS technology.

- EDA Tools: Familiarity with industry-standard backend tools from Synopsys (ICC2/Fusion Compiler), Cadence (Innovus), or Mentor Graphics.

- Scripting Languages: Proficiency in Tcl, Perl, or Python for automation and data parsing. [1, 2, 3]

If you'd like, let me know:

- Your experience level (fresher vs. experienced engineer)

- Whether you need this for hiring or interview preparation

Pay: From ₹15,000,000.00 per year

Benefits

- Paid sick time

- Paid time off

- Provident Fund

Work Location: In person

📌 VLSI DFT Lead & PD Lead Engineer (Bengaluru)
🏢 VK MIndset
📍 Bengaluru