Role Summary
Lead architecture, integration, and verification strategy for high-speed connectivity IPs and chiplet interconnect solutions.
Key Responsibilities
Define PCIe/CXL/ UCIe subsystem architecture.
Drive protocol compliance strategy.
Review integration architecture and performance requirements.
Lead interoperability and compliance planning.
Guide verification and validation teams.
Interface directly with customer architects.
Support roadmap and future standard adoption.
Must Have
12–20+ years in protocol/IP development.
Deep expertise in PCIe Gen4/5/6.
UCIe architecture expertise.
Chiplet ecosystem experience.
Strong knowledge of protocol stack and LTSSM.
Experience with root complex, endpoint, switch architectures.
Experience integrating PCIe into large SoCs.
Strong architecture and verification background.
Knowledge of SerDes architecture.
Positive to Have
CXL protocol knowledge.
HBM integration.
Protocol compliance testing.
System-level performance modeling.
Interested candidates please share your resume at [email protected]

📌 RTL Design (Bengaluru)
🏢 Capgemini Engineering
📍 Bengaluru