Experience: 2-5 Years

Location: Bangalore

Notice Period: Immediate to 15 days

Job Summary

We are looking for highly motivated Standard Cell Layout Design Engineers to support the development, optimization, verification, and release of semiconductor standard cell libraries. The role involves close collaboration with Circuit Design, CAD, Characterization, Physical Verification, Library Architecture, and Technology teams to deliver high-quality standard cells meeting Power, Performance, Area (PPA), reliability, manufacturability, and signoff requirements.

Candidates should possess strong hands-on experience in custom layout design and physical verification, with solid exposure to planar CMOS technology nodes (180nm, 130nm, 90nm, 65nm, 40nm, 28nm). Exposure to FinFET technologies (16nm, 7nm, 5nm, etc.) is a plus.

Key Responsibilities

-Design, implement, and optimize transistor-level layouts for standard cell libraries, including combinational, sequential, level shifter, isolation, ESD, power management, and special-purpose cells.

-Ensure compliance with process design rules and optimize layouts for area, performance, and power.

-Perform physical verification and signoff activities, including DRC, LVS, ERC, and antenna checks, and independently debug violations.

-Drive layout quality by improving pin accessibility, routing robustness, cell abutment compatibility, and EM/IR robustness, while conducting layout reviews and quality audits.

-Support library development, maintenance, release, validation, ECO implementation, and issue resolution involving OA databases, GDSII, and LEF abstracts.

-Develop automation solutions to improve productivity and quality and contribute to methodology and CAD flow enhancements.

-Participate in technical reviews and cross-functional project execution.





Required Technical Skills

Strong understanding of

CMOS device fundamentals

Standard cell architecture and layout methodologies

Transistor-level custom layout design

Layout Dependent Effects (LDE)

Parasitic-aware layout optimization

Hands-on experience with one or more planar CMOS technology nodes, including knowledge of process design rules, layout practices, manufacturability, reliability, yield, and DFM considerations.

Experience with:

Cadence Virtuoso / Layout XL

Siemens Calibre

OpenAccess (OA), GDSII, LEF/DEF, CDL/SPICE

Preferred Skills

Exposure to FinFET technologies, including multi-patterning awareness and advanced design-rule constraints.

Knowledge of SKILL, Shell scripting, automation frameworks, regression methodologies, and quality-check frameworks.

Basic understanding of AI/ML concepts and experience using AI-powered engineering productivity tools.

Educational Qualification

Bachelor's or Master's degree in:

Electronics Engineering

Electrical Engineering

VLSI Design

Microelectronics

Semiconductor Engineering

Key Competencies

Robust analytical, debugging, and problem-solving capabilities.

Excellent attention to detail and quality.

Ability to independently own and drive assignments.

Effective communication and teamwork skills.

Ability to thrive in a fast-paced semiconductor development environment.

Strong learning mindset, adaptability, and continuous improvement orientation.

Ideal Candidate

- A self-driven Standard Cell Layout Engineer with 2-5 years of experience, strong planar CMOS layout expertise, solid physical verification knowledge, and the ability to independently develop signoff-quality layouts. Exposure to FinFET technologies, automation, and AI-assisted engineering workflows will be considered an added advantage.

📌 Standard Cell Design Engineer (Bengaluru)
🏢 Endivite Technologies
📍 Bengaluru