STA Engineer ASIC Full Chip Timing Analysis (Bengaluru)

STA Engineer ASIC Full Chip Timing Analysis (Bengaluru)

29 Aug
|
Agile Ventures
|
Bengaluru

29 Aug

Agile Ventures

Bengaluru

HBM Blocks

Operational-based clock creation.

Experience required in deep timing analysis.

Tools: PrimeTime, virtuse symatic

Develop timing constraints and perform Static Timing Analysis (STA).

Schematic Tracing

Full Chip Timing Analysis

Hands-on experience in full-chip level timing analysis.

ASIC Background

Strong ASIC design/verification background preferred.

Valuable to have: Experience with Virtuoso Schematic tracing.

Experience

Strong profile with 4+ yrs' experience.

Minimum experience: 4 years.

Qualification

B.E. / M.Tech

📌 STA Engineer ASIC Full Chip Timing Analysis (Bengaluru)
🏢 Agile Ventures
📍 Bengaluru

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