29 Aug
|
BITSILICA
|
Hyderabad
29 Aug
BITSILICA
Hyderabad
- 10+ yrs of experience in DFT architecture, scan Insertion, compression at core level and SoC level.
- Experience in ATPG pattern generation, coverage analysis
- Experience with timing and no-timing simulations
- Experience in Memory-BIST
- Have understanding of SSN architecture, clock architecture, OCC
Location: Hyderabad and Bangalore
📌 Senior Staff Engineer - DFT (Hyderabad)
🏢 BITSILICA
📍 Hyderabad