Job Title: VLSI Physical Design Intern

About Semifive

Founded in Seoul in 2019, SEMIFIVE is basing its foundation on Korea’s semiconductor design competency that was amassed for more than 20 years. With expertise spanning front-end to back-end design, SEMIFIVE has become the fastest growing silicon design company that offers the most comprehensive design solutions. SEMIFIVE’s core business is its innovative SoC Platform that enables low-cost and high-efficiency SoC design, and also provides full turnkey silicon design services for global customers.

As the cost of developing SoC and the demand for customized silicon continue to grow rapidly, SEMIFIVE’s SoC Platform plays a critical role in turning innovative ideas into silicon. SEMIFIVE works closely with global technology leaders and is rapidly emerging as The New Global Hub of Custom Silicon.

Semifive India Design Centre, headquartered in Bangalore, is a rapidly growing capability centre responsible for delivering complex, multi-node SoC programs for global customers across the US, Europe, and Asia. The India team owns RTL-to-GDS execution, including physical implementation, timing, power, and signoff for turnkey silicon programs.

Job Summary

We are looking for a highly motivated VLSI Physical Design Intern to join our Physical Design team for a 6-month internship. This internship provides hands-on exposure to full-chip and block-level physical design implementation in advanced technology nodes. The candidate will work closely with experienced PD engineers and gain industry-level expertise in the complete ASIC implementation flow.

Location

Bangalore

Duration

6 Months

Eligibility

M.Tech (ECE / VLSI / Microelectronics) – Final Year or Recent Graduates

Key Responsibilities

Physical Design Implementation





Assist in floorplanning, placement, CTS, routing, and physical verification.

Support timing closure and congestion analysis.

Perform DRC/LVS checks and debug violations.

Work on power planning and IR drop analysis.

Support ECO implementation and timing fixes.

Run multi-threaded tool flows and analyze QoR reports.

Collaborate with synthesis, STA, and backend teams.

Required Skills

Strong understanding of ASIC Physical Design.

Strong CMOS fundamentals and digital design knowledge.

VLSI process knowledge.

Familiarity with industry-standard tools such as:

- Synopsys ICC2
- PrimeTime
- Fusion Compiler (preferred)

Basic scripting knowledge in Tcl / Shell / Python.

Preferred Qualifications

Academic project in Physical Design or ASIC flow.

Exposure to advanced nodes (16nm / 7nm / 5nm) is a plus.

Understanding of timing closure concepts.

Exposure to Physical Verification.

Understanding of power analysis and signal integrity basics.

What You Will Gain

Hands-on industry experience.

Exposure to real tape-out setting.

Mentorship from experienced PD engineers.

Opportunity for full-time conversion based on performance.

Why Join Us?

At Semifive, the SoC PnR Lead plays a pivotal role in delivering first-time-right silicon. Unlike traditional large semiconductor companies where physical design roles can be narrowly scoped, Semifive offers broad ownership and real technical influence across the entire RTL-to-GDS flow.

You will work on multiple cutting-edge SoCs, partner with world-class teams across geographies, and help shape the physical design methodologies of a rapidly growing global organization.

This role offers the opportunity to define how complex silicon is physically realized at Semifive, while mentoring the next generation of physical design leaders.

📌 Physical Design Intern (Bengaluru)
🏢 SEMIFIVE
📍 Bengaluru