Company Description LeadIC Design Pvt Ltd is a VLSI engineering company that accelerates semiconductor innovation through full-stack chip design expertise. Founded in 2018, LeadIC has become a trusted partner for global semiconductor organizations, supporting the complete chip development lifecycle with robust technical ownership and flexible engagement models. With engineering teams across India and Canada, the company delivers high-quality, product-focused design services across custom layout, analog/mixed-signal, digital, verification, and physical design.

LeadIC emphasizes an engineering culture built on ownership, rigorous quality practices, and scalable offshore teams aligned to client roadmaps. Long-term partnerships with leading semiconductor companies reflect the reliability, depth of expertise, and value that LeadIC brings to complex silicon programs.

Role Description We are looking for an experienced Physical Design Engineer with 4+ years of hands-on experience in digital physical design implementation. The candidate should have strong expertise in Cadence Innovus and experience in taking designs from netlist to GDSII, including implementation, timing closure, physical verification, and sign-off activities.

Key Responsibilities

- Perform end-to-end Physical Design implementation from netlist to GDSII.
- Work on Floorplanning, Power Planning, Placement, CTS, Routing and Physical Optimization.
- Perform timing analysis and timing closure for setup and hold violations.
- Analyze and resolve congestion, transition, capacitance, fanout and IR-related issues.
- Perform CTS implementation and clock optimization.




- Execute post-route optimization for timing, power and area (PPA).
- Work closely with STA, RTL, DFT, synthesis and physical verification teams to resolve implementation issues.
- Perform ECO implementation and incremental optimization.
- Analyze physical design reports and debug implementation issues.
- Ensure design quality and adherence to DRC/LVS and sign-off requirements.
- Support physical verification and final GDSII/tape-out activities.

Mandatory Skills
- 4+ years of hands-on experience in Physical Design.
- Strong experience with Cadence Innovus – Mandatory.
- Good understanding of the complete RTL-to-GDSII flow.
- Hands-on experience in:
- Floorplanning
- Power planning
- Placement
- Clock Tree Synthesis (CTS)
- Routing
- Post-route optimization
- Timing closure
- ECO implementation
- Strong understanding of Setup/Hold timing concepts.
- Experience working with MMMC (Multi-Mode Multi-Corner) scenarios.
- Good understanding of LEF/DEF, Liberty, SDC and SPEF.
- Familiarity with Physical Design constraints and sign-off methodologies.
- Strong debugging and problem-solving skills.

Good to Have
- Experience with advanced technology nodes / FinFET.
- Exposure to physical verification and sign-off flows.
- Knowledge of Calibre DRC/LVS.
- Exposure to PrimeTime/Tempus for STA.
- Knowledge of RedHawk/Voltus for power integrity analysis.
- Experience with low-power designs and multi-voltage domains.
- Scripting knowledge in TCL, Perl or Python.
- Experience in block-level and/or full-chip implementation.
- Exposure to IR drop, EM and signal integrity analysis.

📌 Physical Design - 4+ Years - Bangalore Location (Bengaluru)
🏢 leadIC Design
📍 Bengaluru