Location - Hyderabad

Exp - 2 to 8 yrs

Availability - 0 to 30 days

Interested candidate apply at [email protected]

CCTC-

Exp CTC-

Notice Period -

CU Location -

Open to hyd -

Experience: 5yrs to 8yrs.

Hands-on experience in developing/understanding building block schematics, memory schematics, running circuit simulation with spice simulators, DC analysis, transient analysis.

Experience in deciphering circuit behavior from schematics.

Familiarity with circuit characterization, timing libraries - files and formats, timing arcs

Experience in Verilog MOS switch level models and netlist simulation with zero delay, unit delay, and path delay simulations.

Familiarity with static timing analysis

Hands-on experience in Gate level simulations with SDF back annotation.

Debug SDF annotation issues and ensure good annotation coverage.





Hands-on experience with latch based designs and their timing requirements.

Debugging Gate level simulation failures and root causing the failures to actual circuits. Accomplish what-if analysis by doing the change and making sure the fix can solve the issue.

Hands-on knowhow of System Verilog Assertions to specify expected design behavior

Familiarity with UVM is a plus

Solid communication skills, with the ability to convey complex technical concepts to other design peers in verbal and written form.

Gate level simulation, spice correlation, Debug failures and provide fixes at gate or transistor level - as applicable

📌 Hiring GLS Design Verification Engineers -HYD Mirafra Technologies (Hyderabad)
🏢 Mirafra
📍 Hyderabad