Among. The top 4 IT companies, in India ranked by market capitalization and revenue ASIC RTL Lead Bangalopre / Hyderabad / Kochi Mandatory Skill : (RTL Design, RTL Coding & Integration, RTL quality checks (Lint, CDC), IP, targeted for SOC, Static checks, Protocols - PCIe, DDR, Ethernet, I2 C, UART, SPI)Senior ASIC Engineer (IP RTL design targeted for SOC, Static checks, some basic protocols)Expertise in So C subsystem/IP design Expertise in IP design, Subsystem/Cluster and So C level integration using Verilog/System Verilog In depth knowledge on RTL quality checks (Lint, CDC)Knowledge of synthesis and low power is a plus Positive understanding of AMBA bus protocols (AXI, AHB, ATB, APB)Good understanding of timing concepts Knowledge of one or more of the interface protocols a. PCIe b.

DDR c. Ethernet d. I2 C, UART,



SPIExpertise in setting up and using tools like a.

Spyglass

Lint/CDC b. Synopsys DC c. Verdi/Xcellium Understanding of scripting languages like Make flow, Perl ,shell, python etc Understanding of processor architecture and/or ARM debug architecture is a plus Able to help and debug issues for multiple subsystems Able to create/review design documents for multiple subsystems Able to support physical design, verification, DFT and SW teams on design queries and reviews Skills So CPCIe DDREthernet LPDDRVerilog System Verilog Xcellium CPUARMRISC-VContact Udaymuday_bhaskar@ Mulya Technologies"Mining the Knowledge Community"

📌 Asic Rtl Design Lead (Bangalore Metropolitan Area)
🏢 Mulya Technologies
📍 Bangalore Metropolitan Area