AIML Pipeline / Dataflow Design Lead AIML Pipeline / Dataflow Design Lead Location: Bangalore, India | Company: LTSCT — L&T; Semiconductor Technologies Limited Reporting To: Chandra — Senior Architect, DC HW Systems | Experience: 10 years (mandatory) Role Summary We are hiring two AIML Pipeline / Dataflow Design Leads to implement the BFOS-MPE (Broadcast-Fed Output-Stationary Matrix Processing Engine) — the compute heart of xPU. You will own the compute datapath, the broadcast network, PE array control, sparsity engines (SWS), and dual-mode (matrix GPU) switching. You will also own the LLVM interface to the xPU.

Key Responsibilities Own micro-architecture and RTL of the BFOS-MPE compute datapath — dual 256×256 PE arrays (65,536 PEs each) operating at 2 GHz. Design the broadcast-fed input network and output-stationary accumulation scheme that define the BFOS dataflow. Implement PE array control, sequencing, and the sparsity engine (SWS) for structured/unstructured sparsity acceleration.

Architect dual-mode operation enabling switching between dense matrix (GEMM/convolution) and GPU-style workloads. Drive numerical formats and precision (FP/BF/INT, mixed precision) and validate functional correctness against reference models. Coordinate and integrate contributions into the dataflow codebase and verification plan.

Own performance/utilization modeling, power-efficiency optimization, and PPA closure for the compute engine.



Own the ISA/FW routines for the optimal utilization of the HW compute structures in the xPU; as part of the LLVM development.

Required Skills &

Experience 10 years in compute datapath, DSP, GPU, or AI-accelerator micro-architecture and RTL design. Deep understanding of systolic/spatial arrays, matrix-multiply dataflows (output/weight/row-stationary), and broadcast networks. Robust expertise in RTL (SystemVerilog) for high-throughput arithmetic datapaths and control. Solid grounding in numerical formats and arithmetic (FP32/BF16/FP8/INT8), mixed-precision, and rounding/accuracy trade-offs.

Experience with sparsity acceleration techniques (structured/unstructured, weight/activation sparsity). Familiarity with deep-learning operators (GEMM, convolution, attention) and how they map to hardware. Ability to build and correlate performance/utilization models against RTL and reference software.

Hands-on PPA optimization for large, dense compute blocks. Proficiency in C/C /Python for modeling and verification support. Proven leadership and experience integrating cross-organization/partner engineering contributions.

AI compiler development experience is a definite plus.

Preferred Qualifications Direct experience on a taped-out AI/ML accelerator or tensor/matrix engine. Familiarity with GPU SIMT execution models and matrix vector dual-mode designs. Exposure to ML compiler/graph mapping (MLIR, TVM) and how software drives the datapath. M.Tech/MS/PhD in EE/ECE/CS or equivalent.

📌 AI/ML Pipeline and Dataflow Design Lead (Bengaluru)
🏢 Larsen u0026 Toubro
📍 Bengaluru