This is a full time individual contributor position located in Pune, India.

The qualified candidate will be implementing RTL to GDSII flow for complex design.

The qualified candidate will lead and work on full chip backend integration and physical design including power and bump planning, floorplanning, EM-IR signoff.

The qualified candidate will work on DRC, LVS and other signoff checks (PERC, ESD etc) for seamless tapeout activities.

The qualified candidate is expected to have experience in power and bump planning and support package tapeout activities.

The qualified candidate is expected to have strong experience in EM-IR, signal EM, power grid integrity analysis and signoff.

The qualified candidate is expected to have some scripting knowledge or perl /python etc to improve design efficiency and methodology development.

Collaborate with cross functional teams on timing, power and design optimization.

The successful candidate will be open and willing to both (a) teach best-known-methods to an existing FPGA team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and an open-minded student.

Accountabilities:

- Drive full chip integration, EM-IR, signal EM and physical verification activities and bring best-in-class methodologies to achieve best power, performance, and area.
- Ensuring design quality through all physical design quality checks and signoff.




- Develop strong relationships with worldwide teams.
- Mentor and develop strong partners and colleagues.
- Occasional travel as needed.

Required Skills:

- BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent.
- 10+ years of experience in driving backend integration activities of ASIC blocks and full chip.
- Experience on working with industry standard physical design tools including Innovus, Calibre, Virtuso, voltus, Tempus, conformal etc.
- Independent worker with demonstrated problem-solving abilities.
- Proven ability to work with multiple groups across different sites and time zones.
- The qualified candidate is expected to have some scripting knowledge or perl /python etc to improve design efficiency and methodology development.
- Collaborate with cross functional teams on timing, power and design optimization.
- The successful candidate will be open and willing to both (a) teach best-known-methods to an existing FPGA team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and a open-minded student.

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

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