Job Summary

We're hiring a DFT Lead to own ASIC/SoC test strategy, with a core focus on MBIST and ATPG You'll drive DFT architecture from RTL through tapeout, partner closely with design and physical design teams, and help push our silicon toward best-in-class test coverage and quality.

Responsibilities
Own DFT strategy for one or more SoC/ASIC projects: scan architecture, MBIST, and ATPG.
Architect and debug MBIST for embedded memories (SRAM, ROM, register files), including repair/BISR
Define scan chains and generate high-coverage ATPG patterns (stuck-at, transition, cell-aware)
Partner with RTL and physical design teams to resolve DFT-related timing/congestion issues
Drive DFT sign-off: fault grading, coverage analysis, gate-level pattern validation
Support boundary scan (JTAG) and IJTAG test access infrastructure
Work with test engineering on ATE pattern bring-up and silicon debug
Automate DFT flows via Perl/Python/TCL scripting




Mentor junior DFT engineers and improve team DFT methodology

Qualifications
BS/MS in EE, CE, or related field
5+ years of hands-on DFT experience, with solid expertise in MBIST and ATPG
Hands-on with Synopsys DFT Compiler/TestMAX, Tessent, or Cadence Modus
Experience with memory BIST/BISR and memory IP/compilers
Familiarity with JTAG/IJTAG test access standards
Solid digital design fundamentals (combinational/sequential logic, basic STA)
Scripting proficiency (Perl/Python/TCL)
Gate-level simulation experience for pattern validation
Solid communication and cross-functional collaboration skills.

Nice to Have
Power-aware DFT / low-power scan experience
Advanced node experience (7nm and below)
ATE test program bring-up exposure

Pay: Up to ₹110,000.00 per month

Work Location: In person

📌 Design For Testability Lead Dft Bengaluru
🏢 Go Global Technologies
📍 Bengaluru