STA Verification Engineer (Hyderabad)

STA Verification Engineer (Hyderabad)

30 Aug
|
Source right
|
Hyderabad

30 Aug

Source right

Hyderabad

Position: STA Verification Engineer (BB60FT RM 4355)

Mandatory

Full-chip timing analysis / STA signoff (PrimeTime or equivalent) — 4+ yrs, Mandatory
SDC constraint development (clocks, generated clocks, false paths, multicycle, async) — 4+ yrs, Mandatory
STA flow methodologies & timing closure (setup/hold, recovery/removal, slew, fanout) — 4+ yrs, Mandatory
Tcl/Python scripting for automation and debug — 4+ yrs, Mandatory
HBM/DRAM architecture & memory timing concepts — 4+ yrs, Mandatory

Education: BE or MTech (mandatory)

Key Responsibilities

Lead block-level & full-chip STA signoff for HBM across PVT corners.
Create/validate SDCs, implement clocking solutions, correlate with simulation.
Drive timing closure and automation; mentor team; coordinate with Design/Layout/Verification.

📌 STA Verification Engineer (Hyderabad)
🏢 Source right
📍 Hyderabad

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