SoC Design Director Top30 Semiconductor Organization in the world
Bangalore
Role Overvie w
We are seeking a Digital Design professional with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solution s.
Key Responsibili ties
Design and implement high-performance digital solutions, including RTL development and synthesis.Collaborate with cross-functional teams on IP integration for processor IPs and peripherals
Deep knowledge of processor boot process and peripheral implementation with boot firmware inmind Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤16nm.Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug.Utilize tools from Synopsys/Cadence to ensure first-pass silicon success and apply expertise in UVM-based verification flows
Basic Qualifications / Experience Level
Bachelor’s in Electronics/Electrical engineering (Master's prefe
rred).Minimum 20+ years of digital design experience, with focus on processor, peripherals and full chip implementation.Proven expertise in RTL development, synthesis, and timing closure.Experience with front-end design, gate-level simulations, and design verification.Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused att tude.
Required Ex pertise
Proven expertise in micro-architecture development and RTL development for block level and full-chip designs at advanced
nodes (Experience with front-end design, gate-level simulations,



and supporting design verification through multiple ASIC T/O
cycles .Hands-on experience with processor IP (
ARM/ARC)
Experience of working on PCIe is a must
.Hands-on pre-silicon and post-silicon implementing peripherals for I2C/
SPI/UART
Hands-on experience with complex DMA engines and FW interaction
.Strong proficiency in System Verilog/Verilog and scripting (Pytho
n/Perl)
.Experience with block-level and full-chip design at advanced nodes (≤ 16nm)
.Silicon bring-up and post-silicon debug experience
.Familiarity with industry standard simulation, debug, quality checking and synthesis tools Synopsys/Cadence tools and UVM-based design verification
.Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused a ttitude.
Preferred Experience
Knowledge and experience implementing secure boot and security mechanisms like authentication and attestation
is a plus
.Knowledge of system-level design with ARM/ARC/RISC-V processorssub systems
Experience of working on PCIe/UAL isa big plus
.Understanding of PAD design, DFT, and floor planning
.Experience in synthesis, and timing closure is a big plus
.Experience with NIC, switch, or storage product development
.Familiarity with working in design and verification workflows in a CI/CD setting.
Skils
microarchitecture
"rtl design" / "RTL coding" /"RTL Development" /"Logic design"
Synthesis
"timing closure"
ARM
ARC
PCIe
Verilog
SystemVerilog (SV)
UVM
RISC-V
UAL (UALin k)
NIC / Smartnic
Switch / Ethernet /"Ultra ethernet"
NVlink
CXL
RISC-V
DMA
Networking
"data center"
Contact:Uday
Mulya Technologie s
[email protected]

📌 SoC Design Director (Noida)
🏢 Mulya Technologies
📍 Noida