Project Role : Functional Verification Engineer
Project Role Description : Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like SystemVerilog and UVM. Collaborate with design and architecture teams to identify corner cases and ensure complete functional coverage before tape-out.
Must have skills : SoC Verification
Positive to have skills : NA
Minimum 3 year(s) of experience is required
Educational Qualification : 15 years full time education

Summary:
As a Functional Verification Engineer, a typical day involves designing and implementing comprehensive testbenches to validate the functional accuracy of digital designs at both block and system levels. The role requires creating various types of tests, including constrained-random, directed, and coverage-driven, to thoroughly assess the design's behavior. Collaboration with design and architecture teams is essential to uncover edge cases and guarantee exhaustive functional coverage prior to tape-out, ensuring the reliability and robustness of the final product. This position demands a proactive approach to problem-solving and continuous communication within the project team to meet verification goals effectively.

Roles & Responsibilities:
USB Protocol & Standards Knowledge

- Deep understanding of USB 2.0 (HS/FS/LS), USB 3.2 Gen1/Gen2, USB4 v1/v2 specifications
- Strong knowledge of USB-C connector, Alt Mode (DisplayPort, Thunderbolt), and Power Delivery (USB PD 3.1)
- Familiarity with USB host, device,



and dual-role port (DRP) / OTG operation
- Understanding of USB protocol layers: physical, link, protocol, and application
- Knowledge of USB tunnelling over USB4 (PCIe, DisplayPort, USB 3.2 tunnels)

Verification Methodologies & Simulation

- Proficient in UVM (Universal Verification Methodology) for USB PHY and controller IP verification
- Experience writing SystemVerilog/VHDL testbenches, sequences, and functional coverage models
- Assertion-based verification (SVA) for protocol compliance checking
- Simulation tool experience: Synopsys VCS, Cadence Xcelium, Mentor Questa
- Experience with USB VIP (Verification IP) from Synopsys, Cadence, or Aldec
- Regression infrastructure management and coverage closure methodologies

Validation & Lab Skills

- Post-silicon USB bring-up, enumeration debug, and link training validation
- USB protocol analyser usage: Ellisys, Teledyne LeCroy, Total Phase
- Signal integrity validation: eye diagram analysis, jitter measurement, LFPS signalling
- USB-IF Compliance Test Specification (CTS) execution for USB 2.0, 3.x, and USB4
- Interoperability testing across host controllers, hubs, and USB peripheral devices
- USB Power Delivery policy engine validation and PD compliance testing





Tools & Scripting

- Python or Perl scripting for test automation, log parsing, and results reporting
- Familiarity with version control systems: Git, Perforce
- Experience with EDA tools: Synopsys VC Verification, Cadence Incisive/Xcelium
- SPICE / AMS simulation exposure for USB PHY signal integrity analysis desirable

- Expected to perform independently and become an SME.
- Required active participation/contribution in team discussions.
- Contribute in providing solutions to work related problems.
- Assist in documenting verification plans and results to support project milestones.
- Support junior team members by sharing knowledge and providing guidance.
- Engage in continuous learning to stay updated with industry best practices and verification methodologies.

Professional & Technical Skills:

- Must To Have Skills: Proficiency in SoC Verification.
- Experience with SystemVerilog and Universal Verification Methodology for testbench development.
- Strong understanding of digital design principles and verification techniques.
- Ability to develop constrained-random, directed, and coverage-driven tests.
- Familiarity with simulation tools and debugging methodologies.
- Capability to collaborate effectively with cross-functional teams including design and architecture.

Additional Information:

- The candidate should have minimum 3 years of experience in SoC Verification.

- This position is based at our BDC6F - SEZ office.

- A 15 years full time education is required.

15 years full time education

📌 Functional Verification Engineer (India)
🏢 Accenture
📍 India