Job Description Lead Physical Design Engineer
n Location: Bengaluru
n Experience: 6–12 Years
n Role Overview
nWe are looking for a Lead Physical Design Engineer with strong hands-on experience in full-chip Physical Design and Cadence Innovus . The role involves owning critical stages of the physical implementation flow and driving design closure across PPA, timing, power, and physical signoff .
n Key Responsibilities
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- Own full-chip physical design from netlist-to-GDSII, including floorplanning, placement, CTS, routing and physical optimization.n
- Drive timing closure across hierarchical/full-chip designs, including setup/hold analysis and ECO implementation.n
- Robust hands-on expertise with Cadence Innovus for implementation and optimization.n
- Perform floorplan, power planning, placement, CTS, routing and congestion optimization .n
- Debug and resolve timing, congestion, DRC, LVS and routing issues .n
- Work closely with STA, RTL, synthesis, DFT, power and signoff teams to achieve design closure.n




- Execute MMMC-based implementation and optimize designs across multiple PVT scenarios.n
- Drive physical and timing ECOs through final signoff.n
- Analyze and improve PPA while maintaining design robustness and signoff quality.n
- Contribute to flow improvement, automation and methodology development using Tcl/Python/Perl .n

n Required Qualifications
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- 6–12 years of hands-on experience in Physical Design/Physical Implementation .n
- Strong full-chip Physical Design experience with ownership of large and complex SoCs.n
- Expert-level hands-on experience with Cadence Innovus .n
- Strong understanding of floorplanning, placement, CTS, routing, optimization and ECO flows .n
- Solid knowledge of STA, MMMC, timing constraints and timing closure .n
- Experience with congestion, IR/EM, DRC/LVS and physical signoff .n
- Strong understanding of low-power design concepts and multi-voltage implementation is preferred.n
- Proficiency in Tcl

📌 Lead Physical Design Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru