Job Description Lead Physical Design Engineer
N Location: Bengaluru
N Experience: 6–12 Years
N Role Overview
NWe are looking for a Lead Physical Design Engineer with strong hands-on experience in full-chip Physical Design and Cadence Innovus . The role involves owning critical stages of the physical implementation flow and driving design closure across PPA, timing, power, and physical signoff .
N Key Responsibilities
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- Own full-chipphysical design from netlist-to-GDSII, including floorplanning, placement, CTS, routing and physical optimization. N
- Drive timing closure across hierarchical/full-chip designs, including setup/hold analysis and ECO implementation. N
- Strong hands-on expertise with Cadence Innovus for implementation and optimization. N
- Perform floorplan, power planning, placement, CTS, routing and congestion optimization . N
- Debug and resolve timing, congestion, DRC, LVS and routing issues . N
- Work closely with STA, RTL, synthesis, DFT, power and signoff teams to achieve design closure. N




- Execute MMMC-based implementation and optimize designs across multiple PVT scenarios. N
- Drive physical and timing ECOs through final signoff. N
- Analyze and improve PPA while maintaining design robustness and signoff quality. N
- Contribute to flow improvement, automation and methodology development using Tcl/Python/Perl . N

n Required Qualifications
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- 6–12 years of hands-on experience in Physical Design/Physical Implementation . N
- Robust full-chip Physical Design experience with ownership of large and complex SoCs. N
- Expert-level hands-on experience with Cadence Innovus . N
- Strong understanding of floorplanning, placement, CTS, routing, optimization and ECO flows . N
- Solid knowledge of STA, MMMC, timing constraints and timing closure . N
- Experience with congestion, IR/EM, DRC/LVS and physical signoff . N
- Strong understanding of low-power design concepts and multi-voltage implementation is preferred.

📌 Lead Physical Design Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru