30 Aug
|
ACL Digital
|
Hyderabad
30 Aug
ACL Digital
Hyderabad
Lead FPGA/ASIC Verification Engineer
Location: Hyderabad
Experience Required: 10 to 20+ years
Notice Period: 0 to 30 days (Strictly)
Key Skills:
12+ years in FPGA/ASIC functional verification with a focus on C-based or embedded software-driven pre-silicon verification.
Experience with RISC-V, ARM-based SoCs, or embedded CPU verification.
Developing C/C++ testcases and verification frameworks for FPGA/SoC verification.
Solid knowledge of FPGA architectures, SoC subsystems, memory architectures, interrupts, DMA, boot flows, and embedded processors.
Scripting in Python, Shell, Perl, and TCL.
If either of these roles aligns with your background, please reply with your updated CV, current CTC, expected CTC, and official notice period.
Interested candidates can apply directly, and please feel free to refer your friends or network!
📌 Design Verification Lead Hyderabad
🏢 ACL Digital
📍 Hyderabad