Memory Layout EngineerExperience: 4–8 yearsLocation – BangaloreQualifications:Bachelor's or Master's degree in Electrical Engineering,

Technology Nodes: TSMC/Samsung – 2nm, 3nm, 5nm, 7nm, and GF nodesKey Skills & Responsibilities:Hands-on experience in layout of memory blocks like control logic, sense amplifiers, I/O blocks, bit cell array, decoders, etc.Solid experience in SRAM/DRAM, memory compiler IPs, and memory periphery circuitsExpertise in top-level memory integration, DRC, LVS, density verification, and physical closureUnderstanding of IR/EM challenges in memory layoutsProficiency with Cadence/Synopsys tools for layout and Mentor/Cadence/Synopsys tools for physical verificationExposure to ultra-deep sub-micron design challenges and DFM guidelinesKnowledge of memory architecture, bitcell layout concepts, and FinFET design rulesAbility to optimize layout for area, power, speed, yield, and manufacturabilityCollaboration with circuit design, verification, PDK, and methodology team

📌 Memory Layout Engineer (Mumbai)
🏢 Tech Mahindra
📍 Mumbai