LTTS is looking for DV engineers with 7+ years of experience for lead role...detailed JD is below mentioned.8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologiesExperience in development of UVM based verification environments from scratchExperience in architecting and implementing Design Verification infrastructure and executing the full verification cycleExperience with verification of ARM/RISC-V based CPU sub-stems or SoCsExperience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, EthernetExperience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environmentsExperience with revision control stems like Mercurial(Hg), Git or SVN