Lead Synthesis EngineerLocation:

Bengaluru, IndiaExperience:

6–12 YearsAbout the RoleWe're looking for a

Lead Synthesis Engineer

to drive RTL-to-Gate implementation for complex SoCs across advanced technology nodes. You'll own synthesis convergence, optimize PPA, and collaborate with RTL, STA, DFT, and Physical Design teams to deliver high-quality silicon.What You'll DoDrive RTL synthesis using

Synopsys Design Compiler/Fusion Compiler .Optimize designs for

Power, Performance, and Area (PPA)

while meeting timing and design constraints.Develop and debug

SDC constraints , synthesis scripts, and automation flows.Analyze timing, area, power, and QoR reports; resolve synthesis and logical issues.Work closely with

RTL, STA, DFT, Physical Design, and ECO





teams to achieve implementation closure.Support low-power methodologies, LEC, and synthesis signoff across advanced process nodes.What We're Looking For6–12 years of experience in ASIC/SoC Synthesis.Strong expertise in

Synopsys Design Compiler, Fusion Compiler, TCL scripting, and SDC .Solid understanding of

timing constraints, clock gating, UPF, low-power design, LEC, and ECO flows .Experience with advanced technology nodes (7nm/5nm/3nm) is preferred.Solid debugging, problem-solving, and cross-functional collaboration skills.Build next-generation silicon by delivering world-class synthesis quality across cutting-edge SoCs.

📌 Lead Synthesis Engineer (Mumbai)
🏢 Leadsoc Technologies
📍 Mumbai