LEAD BEHAVIORAL MODELING ENGINEER – LATTICE SEMICONDUCTOR INDIALocation:

Hyderabad / Pune / Chennai (India)

JOB SUMMARYWe are seeking a Lead Behavioral Modeling Engineer to join Lattice Semiconductor's FPGA Architecture & Design team. You will lead development of behavioral and architecture models for next-generation low-power FPGA fabrics, own power and timing characterization, and mentor a small modeling team.This is a technical leadership role focused on modeling methodology and design optimization—not traditional product RTL design or verification.

KEY RESPONSIBILITIESDevelop and maintain behavioral models for FPGA fabric elements (CLBs, routing, interconnects, logic blocks)Own power and timing characterization across PVT (Process, Voltage, Temperature) cornersBuild Python-based automation flows for rapid design exploration and PPA analysisLead modeling methodology improvements and drive continuous optimizationCollaborate with architecture, RTL, and circuit design teams to validate design intentMentor and guide modeling engineers on best practices and technical excellenceCorrelate behavioral models against silicon measurements and real chip dataEstablish and communicate modeling standards and documentation

REQUIRED QUALIFICATIONSBachelor's degree in Electrical Engineering or related field (Master's preferred)8+ years in behavioral/architecture modeling or FPGA/ASIC design2+ years of technical leadership experienceProficiency in C++, SystemC,



and Python for model developmentDeep knowledge of FPGA fabric architecture (CLBs, LUTs, routing, interconnects)Robust understanding of power and timing characterization methodologiesExcellent problem-solving and technical communication skillsAbility to lead cross-functional teams and drive collaborative efforts

PREFERRED QUALIFICATIONSMaster's degree (M.Tech, MS) in Electrical/Computer EngineeringPrior experience at semiconductor companiesPublished papers or patents in FPGA modeling or architecture optimizationExperience with ML-based power prediction or on-die sensor integrationTest-chip bring-up and silicon validation experience

WHAT YOU WILL NOT BE DOINGThis role is NOT focused on:Verilog/VHDL/SystemVerilog code development for product designSystemVerilog testbench and formal verificationGate-level or post-layout simulationTraditional Design Verification (DV)Physical design (place & route, floorplanning)

If your background is primarily RTL design or DV, this may not be the right fit.

WHY LATTICE SEMICONDUCTOR?Lattice is the global leader in low-power FPGA solutions for edge AI, automotive, aerospace, and IoT. Your modeling work directly impacts next-generation FPGA architectures and time-to-market for innovative products.

We offer:Deep technical challenge and leadership opportunityCollaborative, innovation-driven cultureHigh-impact products used globallyCompetitive compensation and benefits

📌 LEAD BEHAVIORAL MODELING ENGINEER – LATTICE SEMICONDUCTOR INDIA (Mumbai)
🏢 Lattice Semiconductor
📍 Mumbai