Analog Layout Engineer (Mumbai)

Analog Layout Engineer (Mumbai)

31 Aug
|
Leadsoc Technologies
|
Mumbai

31 Aug

Leadsoc Technologies

Mumbai

Analog Layout EngineerLocation:

Bengaluru, IndiaExperience:

5–10 YearsRoleDesign and implement high-performance

Analog/Mixed-Signal layouts

for advanced-node SoCs. Own layout execution from device level to tapeout while delivering optimal matching, reliability, manufacturability, and first-pass silicon success.What You'll DoDevelop

full-custom Analog Layouts

for high-performance IPs including

PLL, LDO, Bandgap, ADC, DAC, SerDes, DDR PHY, PMIC, Data Converters, IOs, and Clocking Circuits .Perform device placement, routing, floorplanning, shielding, guard ring implementation, common-centroid matching, interdigitation, and parasitic-aware optimization.Drive layout closure for

DRC, LVS, ERC, Antenna, DFM, Density, EM/IR, PERC, and Reliability .Optimize layouts for

matching, noise isolation, IR drop, electromigration, yield, and performance .Collaborate with Circuit Design, Reliability, Physical Verification, and Process teams to achieve PPA and silicon targets.Support layout migration across technology nodes and contribute to layout methodology, automation,



and best practices.What You Bring5–10 years

of hands-on experience in

Analog Full Custom Layout .Robust expertise in

device matching, common centroid, interdigitation, shielding, guard rings, deep N-Well, substrate isolation, and analog routing techniques .Experience with Analog IPs such as

PLL, LDO, Bandgap, ADC/DAC, SerDes, DDR PHY, PMIC, USB, PCIe, MIPI, or High-Speed IOs .Hands-on experience with

Cadence Virtuoso XL/Studio ,

Calibre/PVS/ICV , and extraction tools such as

Quantus

or

StarRC .Strong understanding of

DRC/LVS/ERC, DFM, Antenna, EM/IR, PERC , and advanced-node layout challenges.Experience with

FinFET technologies (16nm/7nm/5nm/3nm)

and physical signoff methodologies.Scripting experience using

SKILL, Tcl, or Python

is an added advantage.PreferredExperience in

Memory Layout ,

High-Speed Interface Layout , or

3DIC/TSV .Exposure to

ESD, Reliability, Low-Power Design , and layout automation.

📌 Analog Layout Engineer (Mumbai)
🏢 Leadsoc Technologies
📍 Mumbai

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