Job Description
Job Title: IO Layout Engineer
n Experience: 3+ Years
n Location: Bangalore
n Employment Type: Full-time
n Industry: Semiconductors / ASIC / VLSI / IO & ESD Design
n Job Summary:
nWe are looking for a highly motivated and experienced IO Layout Engineer to join our custom layout team. The candidate will be responsible for full-custom layout of IO cells, ESD protection structures, and high-voltage interfaces for ASIC/SoC applications in deep submicron and FinFET technologies.
n Key Responsibilities:
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- Perform transistor-level custom layout of various types of IO cells including:n
- Standard IOs (CMOS, LVTTL, LVCMOS, SSTL, HSTL)n
- High-speed and specialty IOs (DDR, USB, PCIe, HDMI, etc.)n
- ESD structures, pad rings, and protection circuitsn
- Work closely with IO circuit designers to interpret schematics and design intent.n
- Ensure robust layout practices for:n
- ESD compliance n
- Latch-up prevention n
- Electromigration (EM)n
- Voltage isolation and guard ring planning n
- Ensure layout meets foundry-specific DRC, LVS,



and antenna rules.n
- Run and close physical verification (DRC, LVS, ERC, ANT) using industry-standard tools.n
- Participate in floorplanning of IO ring and integration with analog/digital blocks.n
- Coordinate with packaging, ESD, and reliability teams to support silicon tapeout.n

n Required Skills and Experience:
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- B.E/B.Tech or M.E/M.Tech in Electronics, Electrical Engineering, or VLSI.n
- 3+ years of hands-on experience in IO and/or ESD layout.n
- Strong understanding of ESD protection concepts and latch-up avoidance.n
- Expertise in Cadence Virtuoso for layout design and implementation.n
- Experience with DRC/LVS tools (Calibre, Assura, PVS).n
- Familiarity with advanced process technologies (28nm, 16nm, 7nm, FinFET, etc.).n
- Good knowledge of layout-dependent effects (LDE), IR drop, and reliability constraints.n
- Attention to detail and solid debugging/problem-solving skills.n



📌 IO Layout Engineer (Bengaluru)
🏢 ACL Digital
📍 Bengaluru