Job Description
Hi All,
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Greetings from Eximietas Design...!
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Eximietas Hiring Principal SoC DFT Engineers | Bengaluru Location.
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Experience: Min 10+Years.
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Locations:- Bengaluru, Hyderabad, Ahmedabad & Visakhapatnam.
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San Jose (Bay Area), USA
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- Eligibility (USA): U.S. Permanent Residents (Green Card holders).
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Job Description:
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We are seeking motivated Design for Test (DFT) professionals to join our growing team. Whether
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you are a hands-on technical lead or an industry veteran with architectural expertise, we offer roles
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that will challenge and grow your skills in advanced silicon testing.
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You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery, across
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complex IP, subsystem, and SOC designs.
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Core Responsibilities:
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End-to-end ownership of the DFT implementation flow from RTL to final pattern sign-off.
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Scan architecture definition and implementation at RTL and gate level, including EDT and
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OCC.
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Execution of block-level ATPG, DRC analysis, and coverage optimization.
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Handling of pattern simulations, including both timing and non-timing simulations.
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SOC-level integration, including pattern retargeting to subsystem and full-chip levels.
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Integration, simulation, and debugging of MBIST, IJTAG, and Boundary Scan (JTAG).
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Independent debugging of DFT simulations and netlist-related issues.
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Close collaboration with design, verification, and physical design teams to ensure DFT
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readiness.
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Ownership of DFT sign-off activities and deliverables.
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Key Responsibilities:
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Develop and implement robust DFT architectures for IP, subsystem, and SOC designs.
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Perform scan insertion, ATPG generation,
and pattern validation at block and top levels.
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Analyze and resolve coverage, DRC, and simulation failures to meet quality targets.
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Define and execute DFT strategies aligned with project requirements and schedules.
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Support pre-silicon and post-silicon test requirements.
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Serve as the DFT point of contact for assigned projects, responsible for verification and test
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readiness sign-off.
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Technical Requirements:
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Must-Have Skills:
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Strong experience in netlist handling and ATPG simulations.
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Proven expertise in block-level and SOC-level pattern retargeting and debugging.
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In-depth understanding of ICL and PDL standards.
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Hands-on experience with at least one major DFT tool suite:
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o Siemens Tessent
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o Synopsys TestMAX / TetraMAX
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o Cadence Modus
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Preferred & Advanced Skills:
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Experience with Streaming Scan Network (SSN).
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Knowledge of Analog and Mixed-Signal DFT methodologies.
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Proficiency with SpyGlass for DFT linting and early-stage analysis.
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Exposure to RTL-level DFT insertion and validation.
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Strong scripting skills (TCL, Python, Perl) for automation.
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What We Offer:
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- Opportunity to work on cutting-edge semiconductor designs and innovative technologies.
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- Collaborative and inclusive work environment.
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- Competitive compensation and benefits package.
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- Professional growth and development opportunities.
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If this chance interests you—or if you know someone suitable—please send your updated resume to:
[email protected].
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Referrals are highly appreciated.
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Best regards,
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Maruthy Prasaad
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Associate VLSI Manager - Talent Acquisition | Visakhapatnam
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Eximietas Design
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[email protected]
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+91 (phone hidden).
📌 Principal SoC DFT Engineer_Bengaluru (Bengaluru)
🏢 Eximietas Design
📍 Bengaluru