Job Description
Lead Synthesis Engineer
nLocation: Bengaluru, India
nExperience: 6–12 Years
nAbout the Role
nWe're looking for a Lead Synthesis Engineer to drive RTL-to-Gate implementation for complex SoCs across advanced technology nodes. You'll own synthesis convergence, optimize PPA, and collaborate with RTL, STA, DFT, and Physical Design teams to deliver high-quality silicon.
nWhat You'll Do
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- Drive RTL synthesis using Synopsys Design Compiler/Fusion Compiler.n
- Optimize designs for Power, Performance, and Area (PPA) while meeting timing and design constraints.n
- Develop and debug SDC constraints, synthesis scripts, and automation flows.n
- Analyze timing, area, power, and QoR reports; resolve synthesis and logical issues.n
- Work closely with RTL, STA, DFT, Physical Design, and ECO teams to achieve implementation closure.n




- Support low-power methodologies, LEC, and synthesis signoff across advanced process nodes.n

nWhat We're Looking For
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- 6–12 years of experience in ASIC/SoC Synthesis.n
- Strong expertise in Synopsys Design Compiler, Fusion Compiler, TCL scripting, and SDC.n
- Solid understanding of timing constraints, clock gating, UPF, low-power design, LEC, and ECO flows.n
- Experience with advanced technology nodes (7nm/5nm/3nm) is preferred.n
- Solid debugging, problem-solving, and cross-functional collaboration skills.n

nBuild next-generation silicon by delivering world-class synthesis quality across cutting-edge SoCs.

📌 Lead Synthesis Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru