Position: Senior Formal Verification Engineer (BB80FT RM 4341)

Role Overview

We are looking for a Senior Formal Verification Engineer to own formal sign-off for complex, highspeed IP blocks and subsystems. The ideal candidate combines deep formal methodology expertise with robust hands-on SystemVerilog/UVM verification experience on complex protocol IPs such as

DDR, PCIe, and Ethernet.

Key Responsibilities

Own end-to-end Formal Property Verification (FPV) for complex IP and subsystem blocks - from test plan and property/assertion development through proof convergence and sign-off

Perform formal connectivity checking, X-propagation, CDC/RDC-adjacent formal analysis, and register/CSR formal verification

Apply advanced formal techniques - abstraction, case-splitting, cut-points, and complexity reduction - to achieve convergence on large, complex designs

Develop and review SystemVerilog Assertions (SVA) for protocol compliance, data integrity, and corner-case behavior on DDR, PCIe, /or Ethernet IP

Complement formal sign-off with strong SV/UVM simulation-based verification where needed - testbench architecture, VIP integration, coverage closure

Collaborate closely with RTL design and architecture teams to debug counterexamples, refine specifications, and drive verification closure

Mentor junior verification engineers and contribute to formal verification methodology and best practices across the team

Required Skills Experience





8+ years of verification experience, with substantial hands-on Formal Verification (FPV) ownership

Strong expertise with industry-standard formal tools - Cadence JasperGold and/or Synopsys VC Formal

Proven experience verifying complex, high-speed protocol IP - DDR, PCIe, and/or Ethernet strongly preferred

Strong System Verilog and UVM expertise, with the ability to work across both formal and simulation-based verification flows

Solid understanding of AMBA protocols (AXI/AHB/APB) and general SoC-level verification concepts

Experience with assertion IP (AIP) development and formal connectivity/architectural verification is a strong plus

Excellent debugging skills and ability to work directly with design/architecture teams to resolve complex issues

Good to Have

Experience with high-speed SerDes or PHY-layer verification

Exposure to low-power verification and UPF-based formal flows

Prior experience mentoring teams or leading formal verification efforts on a project

Job Category: Formal Verification Engineer

Job Type: Full Time

Job Location: Bangalore

Experience: 8+ years

Notice period: 0-30 days

Disclaimer: This job posting and Location has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Sr Formal Verification Engineer (Bengaluru)
🏢 Sourceright Technologies
📍 Bengaluru