Role Overview: We are seeking a

EMIR Engineer

to drive

power integrity, IR drop, and electromigration analysis

for advanced SoC designs. The ideal candidate will have solid expertise in

EMIR sign-off methodology ,

PDN planning , and

chip-package co-design , along with the ability to lead and mentor a team of engineers.

Experience :- 3 Years to 6 Years

Key Responsibilities: Lead

IR drop, electromigration, and power integrity analysis

across multiple blocks and full-chip designs.

Define, implement, and optimize

EMIR sign-off flows

using industry-standard tools (Redhawk, Voltus, Totem, etc.).

Drive

PDN architecture planning

and collaborate with Physical Design teams to ensure robust power delivery.

Perform

chip-package co-simulation

to validate power distribution across die, package, and board.

Review and analyze

EMIR reports , debug issues, and provide recommendations to closure.

Own and automate EMIR flows using

Python/Perl/TCL

scripting.

Collaborate with cross-functional teams (RTL, PD, Verification, Packaging) for design convergence.

Mentor and guide junior engineers in EMIR methodologies and best practices.

📌 Senior EMIR Engineer (Mumbai)
🏢 Leadsoc Technologies
📍 Mumbai